VerilogAE: An Open Source Verilog-A Compiler for Compact Model Parameter Extraction

Abstract

This paper introduces a new open-source Verilog-A compiler, VerilogAE, purpose-built to ease compact model parameter extraction. VerilogAE retrieves all model equations, their dependencies, and relevant model parameters that are defined in a Verilog-A source. This information is made available to users by compiling the Verilog-A source file into a shared library. Herein, the features and design principles of the software and its interface are explained. Then, it is demonstrated how this eases the implementation of parameter extraction methods and steps.

Publication
VerilogAE
Markus Müller
Markus Müller
Research Associate and PhD candidate

My research interests include compact modeling, TCAD and circuit simulation of advanced HBTs.