VerilogAe is a new open-source Verilog-A compiler, purpose-built to ease compact model parameter extraction. It has been developed by my student Pascal as a back-end for our parameter extraction toolkit. VerilogAE retrieves all model equations, their dependencies, and relevant model parameters that are defined in a Verilog-A source file. This information is made available to users by compiling the Verilog-A source file into a shared library.

The features and design principles of the software and its interface are explained in this paper. The project website explains how to use and install this software. If you have problems during installation let me know and I will be glad to help!

Markus Müller
Markus Müller
Research Associate and PhD candidate

My research interests include compact modeling, TCAD and circuit simulation of advanced HBTs.